The U.S. semiconductor industry is facing increasingly difficult challenges as it moves into the production of features at sizes approaching 100 nanometers. The magnitude of some of these challenges has led to their being singled out as industry leaders as “grand challenges” requiring major initiatives to develop solutions using approaches with no historical precedent. Four of the six grand challenges identified in the National Technology Roadmap For Semiconductor include the ability to have affordable scaling, affordable lithography at and below 100 nanometers, new materials and structures, and gigahertz frequency operations on chips.
According to the technology roadmap for semiconductors, the minimum size of features will have to reach 130 nanometers by 2003 to keep pace with the continued doubling of the number of transistors on a chip every 18 months. After 2003, the roadmap indicates a lack of consensus about how to solve the fabrication challenges that lie beyond the 100 nanometer barrier. The problem confronting the industry is that the dominant technology used to make chips, optical lithography, used light to form patterns on silicon. Below 100 nanometers, the wavelength of light typically employed in chip production (193 nanometers and 157 nanometers) are too large to be useful. Several candidate technologies are currently vying for selection as successors to optical lithography. These include extreme ultraviolet lithography (EUV), an electron beam method called scalpel, and x-ray lithography. None has yet emerged as the preferred choice. Since it takes several years to bring the new technology up and running, the large semiconductor manufacturers are becoming increasingly concerned about the time and capital investments that will be required to keep pace with the marketplace demands.
Therefore, it would be desirable to demonstrate the feasibility of fabricating carbon nanotube molecular electronic devices with a nanosize diameter (1-50 nanometers), micro-to-submicron size length (100-1000 nanometers), and gate few nanometers long (1-5 nanometers).
It is widely recognized that the development of molecular electronics based on carbon nanotubes would enable logic devices to be built with billions of transistors and computers that are orders of magnitude more powerful than today's machines. Smart structures in salt grain size computers, for example, could be designed with integrated logic provided by 3-D array of molecular electronic devices. Further advances in wearable computers and other, as yet unforeseen, product possibilities will become more likely. Molecular electronics could also make possible information storage devices with immense capacity. For example, hard disks with storage capacities of terrabytes (1012 bytes) in small products the size of wristwatches with large storage capacities. Before these dreams become a reality, a way must be found to mass produce the molecular electronics devices. Scanning probe methods have proven feasible to fabricate single devices one atom at a time, but no way has yet been found to scale up the process. Chemically based self-assembly processes have also been suggested, but so far only the simplest structures have been built using this method. The problem of combining different materials and assembling molecular electronic devices with specific features remains a daunting challenge.
Theoretical work by Chico et. al. (L. Chico, V. H. Crespi, L. X. Benedict, S. G. Louie, and M. L. Cohen, “Pure Carbon Nanoscale Devices: Nanotube Heterojunctions,” Physical Review Letters, Vol. 76, No. 6, 5 February 1996) has suggested that introducing pentagon-heptagon pair defects into otherwise hexagonal nanotube structure may create junction between two topologically or electrically different nanotubes as bases for nanoscale nanotube devices. Saito (S. Saito, “Carbon Nanotubes for Next Generation Electronic Devices,” Science, Vol. 278, 3 Oct. 1997) describes possible theoretical designs of a carbon nanotube that may function as molecular electronic devices. Those and other similar theoretical works outline the possibility to use carbon nanotubes as molecular devices but is fail to propose a design of such device and a method of its fabrication.
Collins et. al. (P. Collins, H. Bando, A. Zettl, “Nanoscale Electronic Devices on Carbon Nanotubes,” Fifth Foresight Conference on Molecular Nanotechnology) have experimentally demonstrated the rectification properties of single-wall carbon nanotubes. This work also fails to propose a design of carbon nanotube molecular electronic device and a method of its fabrication.
Suenaga et. al. (K. Suenaga, C. Colliex, N. Demoncy, A. Loiseau, H. Pascard, F. Willaime, “Synthesis of Nanopaticles and nanotubes with Well-Separated Layers of Boron Nitride and Carbon,” Science, Vol. 278, 1997) have reported an effort to fabricate nanoscale electronic devices by fabricating concentric nanotubes out of carbon and boron nitride. This concentric design is achieved by filling-in already synthesized carbon nanotube. This design concept may work for a two-terminal device such as diode but cannot be scaled to function as a three-terminal device such as transistor. This work has also failed to explain how such device would function and has not addressed the interconnect problem.
M. Terrones et. al. (M. Terrones et. al., “Controlled production of aligned-nanotube bundles,” Letters to Nature, Vol 388, July 1997) reported on efforts to fabricate horizontally aligned carbon nanotubes that may be used as electronic devices. This effort fails to describe any design of a carbon nanotube molecular device.
Most recent designs of carbon nanotube based molecular electronic devices, such as Dekker et. al. (Tans S J, Verschueren A R M, Dekker C, “Room-temperature transistor based on a single carbon nanotube,” Nature 393: (6680) 49-52, May 7, 1998), consist of a carbon nanotube spanned over two, three, or more metal electrodes. Such device may indeed function as a diode or a transistor but it cannot be scaled and cannot be connected to yet another carbon nanotube transistor.
Most recently Hu et. al. (J. Hu, M. Ouyang, P. Yang, and C. Lieber, “Controlled growth and electrical properties of heterojunctions of carbon nanotubes and silicon nanowires,” Nature, Vol. 399, May 1999) has demonstrated nanoscale electronic device made of joined Si nanowire and carbon nanotube. Although successful, this nano-devices cannot be scaled up and therefore cannot be practically fabricated in a large-scale manufacturing operation.
None of the state-of-the-art research has addressed the scalability of fabricating carbon nanotube based molecular electronic devices, their interconnection, and interconnection between the molecular logic device and the outside world.
Most recently Li et. al. (J. Li, C. Papadopoulos, University of Toronto; J. Xu, Brown University, “Growing Y-junction carbon nanotubes,” Nature, Vol 402, 18 Nov. 1999, pp. 253) has used nanostructured template channels to grow Y-junction carbon nanotube heterostructures from nanochannel alumina template. They first created the top pores with one voltage and then reduced it midway through the electrochemical formation of the pores. They observed that the voltage is proportional to number of pores, therefore, twice as many appeared, most branching from the original pore. This creates Y template. Catalyst was deposited electrochemically at the bottom of the template channels from which carbon nanotubes were grown. Top CNTs were close to twice the diameter of the two bottom branches. They observed that the length of the pores depends on the thickness of the substrate and the length of the Y junction depends on the timing of the current alteration. The method described in this work only addresses formation of large number of evenly distributed templates without control over pattern of the template. Use of template with variable shape to create carbon nanotube that conforms that shape and the method of producing the variable template has been disclosed in U.S. Pat. No. 6,146,227, on page 5, line 43, entitled “Method for Manufacturing Carbon Nanotubes as Functional Elements of MEMS Devices” which is incorporated herein by reference.
The present invention solves all of the above problems that were not addressed by current research. The present invention identifies several designs of carbon nanotube electronic devices made of individual vertically aligned carbon nanotubes embedded in a silicon or aluminum substrate. The advantage of this design is that it is flexible and is suitable for fabrication of two-terminal (diodes) and three-terminal (transistors) carbon nanotube electronic devices, and more complex logic devices made of plurality of carbon nanotube diodes and transistors. Another advantage of the design is that offers true 3-D architecture. Another advantage of the design is that it includes interconnects between the carbon nanotube devices and interconnects with the outside world.
The advantage of the fabrication process is that it can produce patterns of vertically grown carbon nanotubes with control over the location, dimension, and electric properties of the carbon nanotube. Another advantage of the fabrication process is that it can be scaled to produce large number of devices with a batch process. Another advantage of the fabrication process is that it can also fabricate the interconnects. Another advantage of the fabrication process is that vertical growth permits high-density packing of devices. The fabrication technology will enable device densities of 1012 per cm2 (for 3 vertically stacked devices) limited only by lateral interconnect technology (among the carbon nanotubes) and the number of vertically stacked devices. With the help of lateral carbon nanotube interconnects, the technology could provide device densities to 1014 per cm2. Further vertical stacking of the devices would enable magnitudes more of device densities.
The carbon nanotube devices of this invention and their fabrication process are suitable for large-scale manufacturing and interconnection of molecular electronic devices in a “salt-grain” size integrated circuit. This large-scale, low-cost approach will provide extremely fast, low-power, ultra-high-density logic and memory devices which operate at room temperature. The resulting product possibilities include fast, multi-gigaflop processors, smart structures, wearable computers, random access memories with terabyte (1014 bytes) capacities, and other exciting new market opportunities.